The present invention relates to a memory addressing device for data processing apparatus comprising a memory (RAM), a central processing unit (CPU) capable of generating address signals for a first memory location, and a memory control unit (MCU) capable of converting the address signals into a memory address code to address the location, and in which the central processing unit may be activated for a burst transfer of data from a series of locations disposed in a predetermined order with respect to the first location.
In known machines of this type, a cycle of reading or writing an element of data from or to a memory location requires an addressing period (T1) in the memory control unit for the addressing of the location and a transfer period (T2) to load the data element to be written, or, as the case may be, to retrieve the stored data element.
The burst addressing of a series of memory locations requires that the read or write cycles comprise a single addressing period for the first location, followed immediately by a series of transfer periods solely for the transfer of data from the other locations. The memory control units available at low cost at the present time are not, however, capable of carrying out multiple addressing independently of the central processing unit or of enabling the CPU to transfer the data in burst mode.